The central processing unit (CPU) of a data processing system is the portion of the system where data manipulation, logical and arithmetic operations and other data alteration take place. The physical and logical interconnection of the elements of the CPU, the arithmetic logic unit and various registers and multiplexers in a CPU is known as a data path.
Most prior art CPU's have a single data path architecture; that is, they are organized such that the flow of data through the CPU occurs along a single path.
Some prior art CPU's are designed with multiple data paths. These CPU's have used numerous multiported registers in their implementation. However, such arrangements have required the use of large multiplexers. For instance, in a CPU having thirty registers, each multiplexer would be constructed having a thirty-wide input set so as to be capable of servicing all of the registers.
In addition, prior art CPU's may or may not be arranged in a pipelined configuration, i.e., in two or more stages from a timing standpoint such that the execution of a single microinstruction line proceeds in several steps through the data path. Pipelined architecture enables a faster throughput of data through a CPU by allowing portions of different consecutive instructions to be executed simultaneously. For example, while a later phase or rank of a first instruction is being executed, an earlier phase or rank of a second instruction may also be executed.
The data path implementations of the prior art known to the inventors as described above have proved adequate to the task; however, each suffers from one or more of the following drawbacks. Multiple data path CPU's which use multiported registers and multiplexers are usually characterized by a relatively large parts count due to the use of wide multiplexers. In addition, the use of such multiplexers has a limiting effect on the cycle time of the CPU since it is generally true that the wider the multiplexer the longer its associated selection time must be.
Prior art CPU's which are not organized in a pipelined manner are generally not capable of the same instruction throughput rate which pipelined machines are capable.
Another feature of multiple data path prior art CPU's which utilize wide multiplexers is the total flexibility to access the contents of more than two data registers simultaneously. This flexibility, however, may most often prove to provide only an illusory performance advantage since statistically the most used operand is the result from the previous operation.
Therefore, despite the availability of the prior art data path implementation schemes there is still room for improvement from both performance and "performance-versus-cost" standpoints.
In most prior art systems portions of the CPU go unchecked or, alternatively, expensive redundant checking hardware is required. Furthermore, prior art CPU's generally require more interconnections between the test logic and the various functional units to perform microbranching.
Accordingly, it is an object of the present invention to provide a CPU data path architecture which overcomes one or more drawbacks of prior art data path architectures.
Another object of the present invention is to provide a CPU data path architecture having multiple data paths.
A further object of the present invention is to provide a multiple data path CPU architecture which minimizes the multiporting of registers and the use of wide multiplexers.
Another object of the present invention is to provide a multiple data path CPU architecture which allows more than one operation to take place in the CPU per instruction cycle.
These and other objects and advantages of the present invention will become apparent to those of ordinary skill in the art from an examination of the specification, accompanying drawings and appended claims.